1. Field of the Invention
This invention pertains to integrated circuits and more specifically to an analog multiplexer cell for accepting both analog and digital input signals to a MOS integrated circuit.
2. Description of the Prior Art
Certain integrated circuits fabricated by the well known MOS processes are adapted to accepting both analog and digital input signals on a single line, i.e., to a particular input pin. In the prior art this pin which may accept analog or digital input signals is connected to a conventional analog multiplexer cell (pass gate). When several of these cells share a common analog bus, this causes erratic values (signal levels) on that bus if any given input pin is used as a digital input and the voltage applied to the input pin exceeds the supply voltage V.sub.CC by voltage V.sub.BE, where V.sub.BE refers to the base-emitter voltage of the lateral PNP (bipolar) parasitic transistor formed by the P-channel MOS transistor in the analog pass gate. Additionally, pin-to-pin leakage can occur, caused by the lateral PNP parasitic transistor in one of the adjacent multiplexer cells which turns on when the voltage on the bus exceeds the value V.sub.CC +V.sub.BE2, where V.sub.BE2 refers to the base-emitter voltage of the lateral PNP parasitic transistor formed by the P-channel MOS transistor in the adjacent cell.
Therefore these prior art problems occur in an input cell to an integrated circuit which can be used in a mixed signal mode where one or several pins (terminals) are used as digital signal input pins and one or several other input pins are used as analog signal input pins and share a common internal bus. If any of the digital input pins have voltages applied which are higher than V.sub.CC +V.sub.BE of the input cell circuitry, these problems occur. This condition is often found for instance in the automotive electronics environment where it is a common practice to connect digital signal inputs to the battery voltage, typically about 15 volts, through a series (current limiting) resistor.
FIG. 1 shows a prior art circuit having the above-described drawbacks. Input A is a signal applied to input pin 12 of a first cell 10. A second signal input B is applied to a second input pin 14 of a second cell 20. Cell 10 includes a digital mode selection NAND gate 18, to which one input terminal of which is applied a Digital Select signal, and the second input terminal of which is connected to pin 12. The analog switch portion of first cell 10 includes a pass gate including an N-channel (MOSFET) transistor N1 connected to a P-channel (MOSFET) transistor P1. The gate terminals respectively of transistor N1 and transistor P1 are connected to an Analog Select signal and the inverse of the Analog Select Signal.
Also inherently present in the analog switch portion of the first cell 10 is a parasitic lateral PNP (bipolar) transistor QP1 having emitter E, collector C, and base B. The base-emitter voltage of QP1 is referred to as V.sub.BE1. The base of transistor QP1 is connected to the supply voltage V.sub.CC. The detail of the second cell 20 is identical to that of the first cell 10 and is not shown except for another parasitic biopolar transistor QP2 shown as having the base emitter voltage V.sub.BE2. The base B of parasitic transistor QP2 is connected to the supply voltage V.sub.CC, The output signal for the pass gate including transistors N1 and P1 is provided on line 22 to a conventional analog circuit block 28 which is the analog portion of the integrated circuit. Similarly, the output signal of the second cell 20 is provided on output line 24 which is connected via a common bus 26 to line 22. Thus line 26 is the common internal bus referred to above. The above-described problem arises when input signal A or input signal B exceed the supply voltage of V.sub.CC by the amount V.sub.BE for any particular cell. The pin-to-pin leakage referred to above is between pin 12 and pin 14.
In FIG. 1 it is to be understood that the lateral parasitic PNP (bipolar) transistor, e.g., QP1, in each cell causes these problems. The vertical parasitic PNP transistor in each cell actually reduces the magnitude of this problem; however the current handling capability of the vertical PNP transistors is substantially reduced by the relatively large substrate resistance and hence is not sufficient to eliminate the problem.
If the voltage on any one of the input pins, i.e. pin 12, exceeds V.sub.CC, the first (conventional) input diode D.sub.1 is forward biased. In addition, the base-emitter junction of lateral PNP transistor QP1 is also forward biased because the base B of transistor QP.sub.1 is connected to the supply voltage V.sub.CC. Thus, transistor QP1 turns on and the voltage on the output line 22 of the pass gate is the voltage of pin 12 minus the collector-emitter voltage (V.sub.CE) of transistor QP1. This results in a base current in the similar lateral parasitic bipolar transistor QP2 of adjacent cell 20.
Since in each cell the P-channel (MOSFET) transistor P1 is fully symmetrical in terms of its drain/source configuration, the terminal of the parasitic transistor QP2 in cell 20 connected to the output line 24 of cell 20 (nominally the collector) assumes the function of the emitter (terminal E) of transistor QP2, as illustrated in FIG. 1. Thus, the parasitic transistor emitter and collector structures are symmetrical, and so the emitter E of QP2 is connected to the output terminal of cell 20. In this case, transistor QP2 of cell 20 turns on. Thus, undesirably a current path is created from the input pin 12 of cell 10 to the input pin 14 of cell 20.
The other above-described problem exists when the signal input B to cell 20 is held low by a pull down resistor (not shown) of a connected external circuit. Then the current from the input signal A to cell 20 generates a voltage drop across that pull down resistor (not shown) which appears on input pin 14 of cell 20. If this voltage drop exceeds the threshold of the digital input buffer gate 18, an erroneous digital value may be read from the input pin 14 of cell 20.